1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the invention relates to a static random access memory (hereinafter referred to as SRAM) of single-bit-line drive type.
2. Description of the Related Art
In recent years, various problems with SRAMs have become obvious as their storage capacity increases and their operating voltage decreases. SRAMs of single-bit-line drive type are known, from which data can be read at high speeds. As such a SRAM, an SRAM of single-ended-bit-line reading type in which cell data is read through bit lines (BLs) only is available (see, for example, K. Zhang et al., “The Scaling of Data Sensing Schemes for High Speed Cache Design in Sub-0.18 m Technologies”, Tech. Dig. Of VLSI Circuits Symp. 2000, pp. 226-227, June 2000).
In the SRAM of this type, the potential of the BLs must be fully swung in order to amplify the cell data. To read the data at a high speed, it is important to limit the number of cells connected to each BL to about 32. However, the limitation to the number of cells leads to an increase in the number by which the BL is divided in the memory cell array. This ultimately results in an increase of the chip size.
As indicated above, the number of cells connected to each BL must be limited to achieve high-speed reading of data, in the conventional SRAM of single-ended-bit-line reading type. Consequently, the number by which the BL is divided will increase, ultimately increasing the chip size.